Modern memory integrated circuits, particularly read/write circuits such as static random access memories (SRAMs) and dynamic random access memories (DRAMs), are becoming quite large in physical size and in the density of memory locations therein. For example, SRAMs with 2.sup.20 addressable locations and DRAMs with 2.sup.22 addressable locations are now readily available. Even with submicron feature sizes, the physical size of the integrated circuit chip containing such memories can be as large as on the order of 180 kmil.sup.2. In addition, many complex microprocessors now include significant amounts of on-chip memory, such as 64 kbytes or more of read-only memory and 64 kbytes or more of random access memory. The physical chip size of some of these modern microprocessors may be as large as on the order of 250 kmil.sup.2.
It is well known that as the minimum feature size in integrated circuit chips becomes smaller, the size of defect that can cause a failure (i.e., the size of a "killing" defect) also shrinks. As a result, especially with large chip sizes, it is more difficult to achieve adequate manufacturing yield as the size of a killing defect reduces. In order to reduce the vulnerability of a relatively large integrated circuit chip to a single small defect, modern integrated circuits utilize spare rows and columns that can be used to replace defective rows and columns, respectively, in the memory portion of the circuit. Substitution of one of the spare rows or columns is conventionally accomplished by the opening of fuses (or closing of antifuses, as the case may be) in decoder circuitry, so that access is made to the spare row or column upon receipt of the address for the defective row or column in the primary memory array. Conventional fuses include polysilicon fuses which can be opened by a laser beam, and also avalanche-type fuses and antifuses
Examples of memory devices incorporating conventional redundancy schemes are described in Hardee, et al., "A Fault-Tolerant 30 ns/375 mW 16K.times.1 NMOS Static RAM", J. Solid State Circuits, Vol. SC-16, No. 5 (IEEE, 1981), pp. 435-43, and in Childs, et al., "An 18 ns 4K.times.4 CMOS SRAM", J. Solid State Circuits, Vol. SC-19, No. 5 (IEEE, 1984), pp. 545-51. An example of a conventional redundancy decoder is described in U.S. Pat. No. 4,573,146, issued Feb. 25, 1986, assigned to SGS-Thomson Microelectronics, Inc., and incorporated herein by this reference.
Of course, these spare rows and columns require additional chip area for their implementation. Indeed, it has been observed that provision of too many spare rows and columns can add, rather than save, manufacturing cost, if the cost of the chip area required for the spare elements and their decoders outweighs the yield improvement achieved by use of the spare elements. Accordingly, the number of spare rows and columns must be selected considering expected defect density. Besides selection of the number of spare elements, effective redundancy schemes must consider the type of defects likely to be encountered, so that the spare elements match the expected failure type and manifestation.
As can be expected, the organization of the memory array is also a large factor in selecting the number of spare elements to be implemented. Many modern integrated circuit memories are of the nibble-wide or byte-wide organization, where data is written to or read from four or eight (or even more) memory cells in a single cycle. This is generally accomplished by associating each primary array column with one of the input/output terminals (in a read/write memory). In addition, the layout of these memories is often done in such a way that a single level mask change (e.g., a metal mask) can change the organization of the input/output of the memory (e.g., by-one, by-four, or by-eight with either common or dedicated input and output terminals).
The implementation of redundant memory elements can become complicated for memories with multiple input/output terminals, as not only must an address be associated with each redundant element but, in the case of columns, each enabled redundant column must also be associated with an input/output terminal. A conventional technique for accomplishing such association is to merely dedicate one or more redundant columns for each of the input/output terminals, for example as described in the above-cited Childs et al. article (". . . eight spare columns organized as two spares with 4 bits/spare . . .", Childs et al., supra, at 550). While the circuitry is simple in this type of arrangement, the repair efficiency for such a scheme is not optimal as more redundant columns would have to be provided than in the case where each redundant column could be assigned to more than one input/output. Of course, assigning only one column per input/output per block would limit the repairability yield (i.e., the fraction of memories built which can be saved by use of the spare columns).
Other conventional memories include techniques for multiplexing redundant columns to one of several input/output terminals. For example, the circuit described in U.S. Pat. No. 4,573,146 cited hereinabove includes fusible links between the redundant column and each input/output line, so that the redundant column is programmed to be in a one-to-one association with the proper input/output terminal. In such an arrangement, however, significant loading is added to the critical data-out path for the redundant column, likely resulting in the accesses of redundant cells being slower than for accesses of primary memory cells. Accordingly, the worst case access time for the memory is degraded by the enabling of redundant elements.
In larger memories (such as 1 Mbit or larger), it is useful to organize the primary memory array into a number of array blocks, for purposes of reducing power dissipation and improving performance. In memories with such block organization, it is contemplated that the implementation of a block of redundant columns will improve the efficiency of the redundancy scheme by reducing the total number of columns required as compared against dedicating a smaller number of columns to each array block, and by allowing the repair of a greater number of defects in any one block than would be possible with dedicated redundant columns for each block. Conventional redundancy input/output selection schemes, such as described in said U.S. Pat. No. 4,573,146, would be especially cumbersome when applied to memories with redundant blocks; in addition, the large number of fuses and pass gates on each data line would present excessive load to the critical data paths, and thus would degrade the memory performance.
It is therefore an object of the present invention to provide improved redundancy efficiency for an integrated memory circuit by allowing selection of one of several input/output terminals for each redundant element, such as a column.
It is a further object of the present invention to provide such a circuit which may place one of several redundant columns in communication with a selected input/output terminal, depending upon the received address value.
It is a further object of the present invention to provide such a circuit which presents minimal loading to the data path and thus little or no performance degradation.
It is a further object of the present invention to provide such a memory in which such improved efficiency is attained without a significant power dissipation penalty.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.